Intel has given a more detailed look at Xeon 7 “Diamond Rapids,” its next data-center CPU platform, at Hot Chips. Tom’s Hardware reports that the chips are set to arrive in the data center in 2027, while The Register says the platform had been expected earlier and is now delayed until 2027. The headline specification is core count. Both Tom’s Hardware and The Register report that the top Diamond Rapids configuration reaches 256 performance cores in a single socket, up from the 192-core figure The Register says had previously been expected for the platform. The design is materially more disaggregated than older monolithic server CPUs. Tom’s Hardware says a full Diamond Rapids system-on-chip includes 16 core chiplets built on Intel 18A-P, four base tiles built on Intel 3-T, and two fabric hub tiles built on Intel 3. The Register describes the same basic split as up to 22 chiplets that can be added or removed depending on the compute, cache, and memory mix Intel needs. Tom’s Hardware reports that Intel calls the main compute units Compute Building Blocks, or CBBs. Each CBB can contain four core chiplets, and each core chiplet can hold up to 16 cores. The core chiplet sits above a base tile that holds the shared last-level cache; Tom’s Hardware’s article body and headline put that cache at up to 1.28 GB. Packaging is central to the design. According to Tom’s Hardware, Intel uses Foveros Direct 3D to bond the compute tiles to the base tiles, and uses UCIe-S to connect the fabric hub tiles to the cores over a copper connection. Tom’s Hardware notes that this is not Intel’s Embedded Multi-die Interconnect Bridge, or EMIB, which has appeared in prior Intel products. The layout also changes how the chip is organized. Tom’s Hardware says Diamond Rapids centralizes memory and input/output while moving the cores toward the edges of the chip, and connects the Compute Building Blocks to two centralized fabric hubs. The outlet says that arrangement could help thermals because the highest-clocked components are no longer concentrated in the center of the package. Not every detail of the CPU core is public. Tom’s Hardware says Intel did not detail the Panther Cove core architecture during the Hot Chips presentation, leaving room for at least one further technical disclosure before launch. The same report says Diamond Rapids brings AVX 10.2 and Intel’s new “fan-out” fabric, but the provided material does not include a deeper performance analysis. The Register frames Diamond Rapids as a high-end, narrower Xeon platform rather than a broad enterprise refresh. It reports that the chip lacks hyperthreading, also known as simultaneous multithreading, and says Intel is not offering eight-channel Diamond Rapids-SP parts. In The Register’s account, that leaves high-end AP variants aimed at high-performance computing workloads. That scope matters for the competitive read. The Register says AMD’s sixth-generation Venice Epyc CPUs will also top out at 256 cores, putting Diamond Rapids in the fight at the top end. But the same report cautions that Diamond Rapids will not compete across every server-CPU segment, because the mainstream SP-class products are not part of this generation as described. Who benefits: HPC customers and platform vendors evaluating very high core-count single-socket systems get a clearer view of Intel’s next top-end Xeon path. Intel also benefits if Diamond Rapids proves its chiplet and packaging approach at scale. Who's exposed: Buyers waiting for mainstream Diamond Rapids-SP parts are exposed to a narrower lineup, according to The Register. AMD remains the named competitive reference point at the 256-core high end, but the provided sources do not establish performance or pricing outcomes.